Integrated circuits (chips) comprise many different components that must have electrical connections therebetween in order to interoperate. Typically, the chip real estate is divided into different regions with each particular component being assigned a particular region of the “floorplan.” For example, a particular region is reserved for a memory controller, another region for a processor core, etc. These regions are referred to as “active regions.” Typically, a thin channel (“non-active region”) separates the active regions. As described below, portions of the non-active region can be reserved for repeaters to improve signal transmission between the components. However, as more of the floorplan is used as active regions for components, less of the floorplan is available as a non-active region. This is true of systems-on-a-chip (SoCs), as well as other integrated circuits.
In order for the different components to interoperate, thousands of electrical connections are needed to route signals between the components. Typically, the signal routes are implemented in metal layers above the chip substrate. A particular signal route often requires one or more repeaters to assure proper signal propagation. For example, the signal route may have an RC delay due to electrical resistance of the metal used for the signal path and capacitive coupling between the metal and other electrical connections. Electrically connecting a repeater to a signal path can reduce or eliminate the RC delay. A repeater may also improve other signal propagation characteristics such as signal shape. Since the repeaters are not at the metal layers used for the signal paths, the signal path is typically routed down to the input and output of a repeater. Unfortunately, determining which repeater to use for each signal route is complex and time consuming. Moreover, the process of routing the signal path to the assigned repeater significantly complicates the overall routing of signal paths.
Typically, the process of assigning repeaters to signal paths and routing the signal paths is iterative. For example, during a floor planning stage, a portion of the channels is reserved for repeaters. This is followed by a first pass at determining signal routes in the metal layers for the needed electrical connections, which generates a “netlist” of electrical connections. Then, an attempt is made to assign repeaters to whatever signal routes need them. However, typically this attempt fails to assign a repeater to each signal route that needs one or more repeaters. Moreover, many of the repeater assignments are poorly optimized in that a significant detour must be made from the signal path to route it to the repeater. In some cases, the locations in the floor plan that are reserved for the repeaters are modified and the process is repeated. The new locations for the repeaters may be based, at least in part, on an analysis of the timing of the signal routes, factoring in the detours to get to the repeaters.
As integrated circuits become more complex and compact, the challenge of routing the signal paths and assigning repeaters becomes more difficult. Further, as integrated circuits become more complex, the channel size becomes smaller. Thus, finding suitable repeaters locations is becoming more difficult.
Another problem with these techniques for routing signal paths is the unpredictability of the correlation between the original routing solution and the final routing solution after the iterations have converged to a final routing solution. Because designers rely on the original routing solution to perform early full chip timing analysis, if the final routing solution does not correlate well with the original routing solution then the early timing analysis will not be valid.
Because of these and potentially other drawbacks, this approach does not provide wholly satisfactory results. Consequently, an improved method and system for routing signal paths and assigning repeaters to signal paths during an integrated circuit design process is desired.